US 2022/0020645 A1 · STRUCTURES AND METHODS OF FABRICATING ELECTRONIC DEVICES USING SEPARATION AND CHARGE DEPLETION TECHNIQUES

Abstract

A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate. Drain electrode contacts are formed over the semiconductor region while gate electrode and source electrode contacts are formed by etching portions of a metallic layer formed over the first side of the substrate.

Claims20

Dependent claims

A method of forming an electronic device, comprising:

forming a plurality of channel structures over a first side of a semiconductor substrate, the plurality of channel structures substantially perpendicular to the first side of the semiconductor substrate;
forming gate dielectric regions over a portion of the plurality of channel structures and planar regions;
forming gate electrode regions over a portion of the gate dielectric regions;
forming source regions and body tie regions on the walls of the plurality of channel structures;
forming dielectric regions over the gate electrode regions to electrically isolate the gate electrode regions from the source regions;
forming a first metallic layer over the first side of the semiconductor substrate;
inducing stress within the semiconductor substrate by annealing and/or cooling the semiconductor substrate and the first metallic layer;
separating a first semiconductor region and the first metallic layer from the semiconductor substrate, wherein the first semiconductor region is a first portion of the semiconductor substrate;
forming backside metal regions over the first semiconductor region, the backside metal regions capable of being drain metal electrode contacts;
and
etching portions of the first metallic layer to form gate metal electrode contacts and source metal electrode contacts.

8 more elements

Dependencies are inferred from the claim text.

Structures and methods of fabricating electronic devices using separation and charge depletion techniques

Life of this patent

Structures and methods of fabricating electronic devices using separation and charge depletion techniques

Life of this patent

Abstract

Claims20