Compression of kernel data for neural network operations

A processor circuit, comprising:

• a matrix access circuit coupled to memory external to the processor circuit, the matrix access circuit configured to read compressed matrix data from the memory;
• a matrix extract circuit coupled to the matrix access circuit, the matrix extract circuit configured to extract uncompressed matrix data from the compressed matrix data, wherein the compressed matrix data includes a mask value for each matrix indicative of one or more locations in the matrix where coefficients are non-zero;
• and
• a computation circuit coupled to the matrix extract circuit to receive the uncompressed matrix data, the computation circuit further configured to perform computation operations using the uncompressed matrix data.

A method of operating a processor circuit, comprising:

• reading, by a matrix access circuit, compressed matrix data from a memory external to the processor circuit, wherein the compressed matrix data includes a mask value for each matrix indicative of one or more locations in the matrix where coefficients are non-zero;
• extracting, by a matrix extract circuit, uncompressed matrix data from the compressed matrix data using the mask value;
• and
• performing, by a computation circuit, computation operations using the uncompressed matrix data.

An electronic device, comprising:

• memory storing compressed matrix data;
• and
• a processor circuit coupled to the memory, the processor circuit comprising
• a matrix access circuit coupled to the memory, the matrix access circuit configured to read compressed matrix data from the memory;
• a matrix extract circuit coupled to the matrix access circuit, the matrix extract circuit configured to extract uncompressed matrix data from the compressed matrix data, wherein the compressed matrix data includes a mask value for each matrix indicative of one or more locations in the matrix where coefficients are non-zero;
• and
• a computation circuit coupled to the matrix extract circuit to receive the uncompressed matrix data, the computation circuit further configured to perform computation operations using the uncompressed matrix data.