Linked miss-to-miss instruction prefetcher

A system for prefetching comprising:

• a processor;
• a long-term storage;
• a cache;
• a prefetch system that includes a linked miss-to-miss (LMTM) table, wherein the LMTM table links a cache miss with a previous cache miss;
• and
• a computer-readable storage medium communicatively coupled to the processor and storing program instructions which, when executed by the processor, are configured to cause the processor to:
• prefetch, in response to a first instruction address (I/A) being included in the LMTM table, a second I/A into the cache.

A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processing unit to cause the processing unit to:

• determine, by a prefetch system, a first access attempt of a first I/A in a cache is a first miss, wherein the first I/A is included in a string of I/A's;
• store the first I/A in a linked miss-to-miss (LMTM) table;
• determine a second access attempt of a second I/A in the cache is a second miss, wherein the second I/A is included in the string of I/A's;
• link, in the LMTM table, the second miss to the first miss;
• and
• prefetch, in response to a third access attempt of the first I/A, the second I/A in the cache.