Mode-specific endbranch for control flow termination

A system comprising:

• memory to store a plurality of instructions;
• and
• a processor coupled to the memory, the processor including:
• decoder circuitry to decode a first single instruction and a second single instruction, the first single instruction to include an opcode to indicate execution of an indirect branch in 64-bit mode is to be terminated, the second single instruction to include an opcode to indicate execution of an indirect branch in 32-bit mode is to be terminated;
• and
• processing logic coupled to the decoder circuitry, the processing logic to, in response to the decoder circuitry decoding the first single instruction in 64-bit mode, terminate a 64-bit indirect branch, and, in response to the decoder circuitry decoding the first single instruction in 32-bit mode, raise a first execution exception, and, in response to the decoder circuitry decoding the second single instruction in 32-bit mode, terminate a 32-bit indirect branch, and, in response to the decoder circuitry decoding the second single instruction in 64-bit mode, raise a second execution exception.

A method comprising:

• decoding a first single instruction, the first single instruction to include an opcode to indicate execution of an indirect branch in 64-bit mode is to be terminated;
• in response to the decoded first single instruction in 64-bit mode, terminating a 64-bit indirect branch;
• in response to the decoded first single instruction in 32-bit mode, raising a first execution exception;
• decoding a second single instruction, the second single instruction to include an opcode to indicate execution of an indirect branch in 32-bit mode is to be terminated;
• in response to the decoded second single instruction in 32-bit mode, terminating a 32-bit indirect branch;
• in response to the decoded second single instruction in 64-bit mode, raising a second execution exception.