US 2022/0019349 A1 · DEMAND MEMORY PAGE SIZE

Abstract

Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.

Claims20

Dependent claims

A method, comprising:

receiving a memory access command indicating a variable memory page size for a memory array comprising a plurality of ferroelectric memory cells;
activating a word line based at least in part on the memory access command, the word line coupled with a row of ferroelectric memory cells of the plurality of ferroelectric memory cells;
applying a voltage bias to a plate line of a plurality of plate lines coupled with the row of ferroelectric memory cells based at least in part on the variable memory page size, the plate line coupled with at least a subset of ferroelectric memory cells of the row of ferroelectric memory cells;
and
accessing data stored in the memory array based at least in part on activating the word line and applying the voltage bias to the plate line.

2 more elements

An apparatus, comprising:

a memory array comprising a row of ferroelectric memory cells;
a word line coupled with each ferroelectric memory cell of the row of ferroelectric memory cells;
a plurality of plate lines each coupled with one or more ferroelectric memory cells of the row of ferroelectric memory cells;
and
a controller coupled with the memory array, the word line, and the plurality of plate lines, the controller operable to:
receive a memory access command indicating a variable memory page size for the memory array;
activate the word line based at least in part on the memory access command;
apply a voltage bias to a plate line of the plurality of plate lines based at least in part on the variable memory page size;
and
access data stored in at least a subset of ferroelectric memory cells of the row of ferroelectric memory cells based at least in part on applying the voltage bias to the plate line.

7 more elements

A system, comprising:

a processor operable to send a memory access request indicating a variable memory page size for a memory array comprising a plurality of ferroelectric memory cells;
a system memory controller coupled with the processor and operable to generate a memory access command based at least in part on the memory access request, the memory access command indicative of the variable memory page size;
and
a local memory controller coupled with the memory array, the processor, and the system memory controller, wherein the local memory controller is operable to:
receive the memory access command indicating the variable memory page size for the memory array;
activate a word line based at least in part on the memory access command, the word line coupled with a row of ferroelectric memory cells of the plurality of ferroelectric memory cells;
apply a voltage bias to a plate line of a plurality of plate lines coupled with the memory array based at least in part on the variable memory page size, the plate line coupled with at least a subset of ferroelectric memory cells of the row of ferroelectric memory cells;
and
access data stored in the memory array based at least in part on activating the word line and the plate line.

6 more elements

Dependencies are inferred from the claim text.

Demand memory page size

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Demand memory page size

Life of this patent

Abstract

Claims20