Power semiconductor devices having multilayer gate dielectric layers that include an etch stop/field control layer and methods of forming such devices

A semiconductor device, comprising:

• a semiconductor layer structure that comprises silicon carbide;
• a gate dielectric layer on the semiconductor layer structure;
• and
• a gate electrode on the gate dielectric layer opposite the semiconductor layer structure,
• wherein the semiconductor device is configured so that a peak electric field in the gate dielectric layer during on-state operation is below a top surface of the gate dielectric layer.

A semiconductor device, comprising:

• a semiconductor layer structure that comprises:
• a silicon carbide drift layer having a first conductivity type;
• first and second silicon carbide wells that each have a second conductivity type in respective upper portions of the drift layer;
• first and second silicon carbide source regions having the first conductivity type in upper portions of the respective first and second wells;
• and
• a JFET region having the first conductivity type between the first and second wells;
• a gate dielectric layer on the semiconductor layer structure, the gate dielectric layer including a silicon oxide base gate dielectric layer that is on the semiconductor layer structure and a capping gate dielectric layer on the base gate dielectric layer opposite the semiconductor layer structure;
• and
• a silicon gate electrode on the gate dielectric layer opposite the semiconductor layer structure,
• wherein the semiconductor device is configured so that during on-state operation a peak electric field value in the base gate dielectric layer is at least 50% greater than a peak electric field value in the capping gate dielectric layer.