Three-dimensional memory and fabricating method thereof

A three-dimensional memory, comprising:

• a memory cell array comprising a plurality of levels stacked in a first direction, wherein a plurality of memory cells are formed in a plurality of lines in each of the levels, wherein each of the memory cells comprises a transistor, and the transistor comprises:
• a first isolation region and a second isolation region formed in a lower layer of the level, wherein the first isolation region is separated from the second isolation region by a first memory film in the lower layer;
• a drain region and a source region formed in a middle layer of the level, wherein the drain region is separated from the source region by a second memory film in the middle layer, and a channel between the drain region and source region is wrapped by the second memory film;
• a first electrode and a second electrode formed in a higher layer of the level, wherein the first electrode is separated from the second electrode by a third memory film in the higher layer;
• and
• a gate electrode formed between the source region and drain region, wherein the first, second, and third memory films are wrapped by the metal gate.

A method for fabricating a three-dimensional (3D) memory, comprising:

• forming a stack with a plurality of levels, wherein each of the levels comprises an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer;
• forming a first trench and a plurality of second trenches along each parallel line in the stack with the levels;
• removing the isolation layers and the metal layers in the parallel lines through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line;
• and
• forming a plurality of memory cells in the parallel lines of the levels, wherein in each of the levels, each of the memory cells comprises a transistor and a channel of the transistor is formed by the semiconductor layer in the corresponding parallel line.