Capacitor, memory device, and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChung-Liang CHENG
Life of this patent
Estimating the term…
Abstract
A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.
Claims20
A device, comprising:
- a substrate;
- a first nanostructure over the substrate, comprising a semiconductor having a first resistance;
- a second nanostructure over the substrate, offset laterally from the first nanostructure, at about the same height above the substrate as the first nanostructure, comprising a conductor having a second resistance lower than the first resistance;
- a first gate structure over and wrapped around the first nanostructure;
- and
- a second gate structure over and wrapped around the second nanostructure.
A device, comprising:
- a first capacitor of a second wafer, the first capacitor comprising:
- a first channel having a first end contacting a first epitaxial region, and a second end contacting a second epitaxial region;
- a first gate structure over and wrapped around the first channel;
- and
- a first contact over and contacting the first epitaxial region;
- and
- a first transistor of a first wafer bonded to the second wafer, the first transistor overlying the first capacitor, the first transistor comprising:
- a second channel having a first end contacting a third epitaxial region, and a second end contacting a fourth epitaxial region;
- a second gate structure over and wrapped around the second channel;
- and
- a backside via contacting the third epitaxial region, and electrically connected to the first epitaxial region.
A method, comprising:
- forming a first semiconductor fin protruding from a substrate;
- forming a first gate structure over the first semiconductor fin;
- forming first channels of the first semiconductor fin by etching regions of the first semiconductor fin exposed by the first gate structure;
- reducing resistivity of the first channels of the first semiconductor fin to below about 100 ohms/square;
- and
- forming first and second source/drain regions on either side of the first gate structure and the first channels.
Dependencies are inferred from the claim text.