Semiconductor package including stacked semiconductor chips

A semiconductor package, comprising:

• a substrate;
• a sub semiconductor package disposed over the substrate, wherein the sub semiconductor package includes a sub semiconductor chip with chip pads on its upper surface, a sub molding layer that surrounds side surfaces of the sub semiconductor chip, and a redistribution conductive layer that is connected to each of the chip pads and extends over an upper surface of the sub molding layer, wherein the redistribution conductive layer includes a signal redistribution conductive layer that extends onto an edge of the sub molding layer with a signal redistribution pad on its end portion and includes a power redistribution conductive layer with a length that is shorter than a length of the signal redistribution conductive layer;
• a sub signal interconnector connecting the signal redistribution pad to the substrate;
• a sub power interconnector extending in a vertical direction under the power redistribution conductive layer to connect the power redistribution conductive layer to the substrate;
• and
• at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate or the sub semiconductor chip.