Package structures having underfills

A package structure, comprising:

• a lower substrate;
• substrate connection terminals on the lower substrate;
• a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate;
• a stiffener on the lower substrate and extending around the semiconductor package;
• a heat spreader on the stiffener, the heat spreader being connected to the stiffener and an upper surface of the semiconductor package;
• first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals;
• and
• a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package, as viewed in the plan view.

A package structure, comprising:

• a lower substrate including upper pads thereon;
• external connection terminals on a lower surface of the lower substrate;
• substrate connection terminals connected to the upper pads;
• a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate, first semiconductor chips and second semiconductor chips on the package substrate, and a first encapsulant covering the package substrate and the first and second semiconductor chips;
• first underfills on the lower substrate, each of the first underfills including:
• an inner portion overlapping the semiconductor package in a vertical direction, the inner portion covering at least one of the substrate connection terminals, and
• an outer portion not overlapping the semiconductor package in the vertical direction, the outer portion covering a corner portion of the semiconductor package in a plan view, and lower surfaces of the inner portion and the outer portion being coplanar;
• and
• a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in the plan view,
• wherein each of the second semiconductor chips includes first to fourth memory chips stacked in the vertical direction, four of the second semiconductor chips being positioned adjacent to each of the first semiconductor chips.