Memory device and manufacturing method thereof

A memory device, comprising:

• a logic die;
• a memory cube, mounted on and connected with the logic die through connectors, wherein the memory cube includes a first tier, at least one second tier, and a third tier, the at least one second tier is located between the first tier and the third tier, the first tier is closest to the logic die, and each of the first tier, the at least one second tier and the third tier includes:
• semiconductor dies laterally wrapped by an encapsulant;
• and
• a redistribution structure disposed on the semiconductor dies and the encapsulant, wherein the semiconductor dies of the memory cube are electrically connected with the logic die through the redistribution structures of the memory cube, the redistribution structure of the first tier includes a thermally conductive layer connected to the logic die, the thermally conductive layer of the first tier extends laterally beyond spans of the semiconductor dies in the first tier, and the thermally conductive layer of the first tier is electrically isolated from the semiconductor dies of the memory cube and the logic die;
• and
• a molding compound, laterally wrapping the memory cube and wrapping around the connectors.

A method, comprising:

• forming first redistribution patterns in a first dielectric layer;
• forming second redistribution patterns electrically connected with the first redistribution patterns on the first dielectric layer with a first material;
• forming a thermally conductive layer electrically isolated from the first redistribution patterns and the second redistribution patterns over the first dielectric layer with a second material different form the first material;
• and
• forming a second dielectric layer over the first dielectric layer, wherein the second redistribution patterns and the thermally conductive layer are embedded in the second dielectric layer.