3d memory device and structure
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Jin-Woo Han, Brian Cronquist
Life of this patent
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Abstract
A semiconductor device, the device including: a first level overlaid by a first memory level, where the first memory level includes a first thinned single crystal substrate; a second memory level, the second memory level disposed on top of the first memory level, where the second memory level includes a second thinned single crystal substrate; and a memory control level disposed on top of the second memory level, where the memory control level is bonded to the second memory level, and where the bonded includes oxide to oxide and conductor to conductor bonding.
Claims20
A semiconductor device, the device comprising:
- a first level overlaid by a first memory level,
- wherein said first memory level comprises a first thinned single crystal substrate;
- a second memory level, said second memory level disposed on top of said first memory level,
- wherein said second memory level comprises a second thinned single crystal substrate;
- and
- a memory control level disposed on top of said second memory level,
- wherein said memory control level is bonded to said second memory level, and
- wherein said bonded comprises oxide to oxide and conductor to conductor bonding.
A semiconductor device, the device comprising:
- a memory control level;
- a first memory level disposed on top of said memory control level,
- wherein said first memory level comprises a first thinned single crystal substrate;
- and
- a second memory level disposed on top of said first memory level,
- wherein said second memory level comprises a second thinned single crystal substrate,
- wherein said first memory level is bonded to said second memory level, and
- wherein said bonded comprises oxide to oxide and conductor to conductor bonding.
A semiconductor device, the device comprising:
- a first memory level,
- wherein said first memory level comprises a first thinned single crystal substrate;
- a second memory level disposed on top of said first memory level,
- wherein said second memory level comprises a second thinned single crystal substrate;
- a memory control level disposed on top of said second memory level,
- wherein said memory control level is bonded to said second memory level, and
- wherein said bonded comprises oxide to oxide and conductor to conductor bonding.
Dependencies are inferred from the claim text.