Semiconductor package

A semiconductor package, comprising:

• a first semiconductor chip;
• a second semiconductor chip on the first semiconductor chip;
• a first connection structure below the first semiconductor chip and comprising a first redistribution structure electrically connected to the first semiconductor chip and having a first surface contacting the first semiconductor chip, the first redistribution structure including a first redistribution layer and a first redistribution via;
• a first pad on a center portion of a second surface of the first connection structure opposite the first surface;
• a second pad on an edge portion of the second surface;
• a second connection structure on the first semiconductor chip and comprising a second redistribution structure electrically connected to the second semiconductor chip and including a second redistribution layer and a second redistribution via;
• a vertical connection structure on at least one side of the first semiconductor chip and electrically connecting the first redistribution structure and the second redistribution structure;
• and
• an electrical connection metal on the first pad on the second surface,
• wherein the electrical connection metal is not on the second pad.

A semiconductor package, comprising:

• a first semiconductor chip comprising a first connection pad;
• a first connection structure below the first semiconductor chip and comprising a first redistribution structure electrically connected to the first semiconductor chip and including a first redistribution layer and a first redistribution via;
• a first passivation layer on the first connection structure and having a testing opening in an edge portion of the first connection structure;
• a second connection structure on the first semiconductor chip and comprising a second redistribution structure including a second redistribution layer and a second redistribution via;
• a second semiconductor chip on the second connection structure and electrically connected to the second redistribution structure, the second semiconductor chip including a second connection pad;
• a vertical connection structure on at least one side of the first semiconductor chip and electrically connecting the first redistribution structure and the second redistribution structure;
• and
• a test pad electrically connected to the first redistribution structure and having a lower surface accessible via the testing opening,
• wherein the first and second redistribution structures and the vertical connection structure provide a test signal path electrically connecting the second connection pad of the second semiconductor chip and the test pad.