Error detection and correction using machine learning

A computer-implemented method for controlling a memory system comprising a memory device and a memory controller including a processor, the method comprising:

• sensing, by the memory controller, outputs from the memory cells in response to a read command from a host;
• performing, by the memory controller, a first correcting code (ECC) operation on a first codeword determined from the sensed outputs;
• and
• when the first ECC operation fails, the method further comprising:
• applying, by the processor, for each selected memory cell among the memory cells, a corresponding one of the sensed outputs and a neighbour voltage of a neighbour memory cell as input features to a machine learning algorithm to generate a second codeword;
• and
• performing, by the memory controller, a second ECC operation using the second codeword,
• wherein the neighbour memory cell is connected to a same one of the wordlines as the selected memory cell.

A memory system, comprising:

• a memory device comprising a plurality of memory cells, a plurality of wordlines, and a plurality of bitlines;
• and
• a memory controller comprising a processor,
• wherein the memory controller is configured to read outputs from the memory cells in response to read command from a host and convert the read voltages into a first codeword, wherein the memory controller is further configured to perform a first error correcting code (ECC) operation on the first codeword,
• wherein the processor is configured to apply, for each selected memory cell among the memory cells, a corresponding one of the read outputs and a pillar voltage of a neighbour memory cell as input features to a machine learning algorithm to generate a second codeword, and the memory controller is configured to perform a second ECC operation using the second codeword, when the first ECC operation fails,
• where the neighbour memory cell is connected to a same one of the bitlines as the selected memory cell.

A computer-implemented method for controlling a memory system comprising a memory device and a memory controller including a processor, the method comprising:

• sensing, by the memory controller, outputs from the memory cells in response to read command from a host;
• performing, by the memory controller, a first correcting code (ECC) operation on a first codeword generated from the sensed outputs;
• and
• when the first ECC operation fails, the method further comprising:
• applying, by the processor, for each selected memory cell among the memory cells, a corresponding one of the sensed outputs and a pillar voltage of a neighbour memory cell as input features to a machine learning algorithm to generate a second codeword;
• and
• performing, by the memory controller, a second ECC operation on the second codeword,
• where the neighbour memory cell is connected to a same one of the bitlines as the selected memory cell.