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US 2022/0013188 A1Published application
Memory device
AssigneeSK hynix Inc.
InventorSang Hwan KIM
Life of this patent
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Abstract
A memory device includes a first pad, a second pad, and a double data rate (DDR) test controller. The first pad may receive a write enable signal. The second pad may receive a data strobe signal. The DDR test controller is connected to the first pad and the second pad and outputs an internal write enable signal and an internal data strobe signal. The DDR test controller generates the internal data strobe signal based on the write enable signal received through the first pad, in at least a portion of a DDR test operation of the memory device.
Claims21
A memory device comprising:
- a first pad capable of receiving a write enable signal;
- a second pad capable of receiving a data strobe signal;
- and
- a double data rate (DDR) test controller connected to the first pad and the second pad and configured to output an internal write enable signal and an internal data strobe signal,
- wherein the DDR test controller generates the internal data strobe signal based on the write enable signal received through the first pad, in at least a portion of a DDR test operation of the memory device.
2 more elements
A memory device comprising:
- a memory cell array including a plurality of memory cells;
- a peripheral circuit configured to perform a program operation, an erase operation, or a read operation on the memory cell array;
- a control logic configured to control an operation of the peripheral circuit;
- and
- a double data rate (DDR) test controller configured to generate an internal write enable signal and an internal data strobe signal for being transferred to the control logic based on signals received from a first pad and a second pad,
- wherein the DDR test controller generates the internal write enable signal based on a first signal received through the first pad and generates the internal data strobe signal based on a second signal received through the second pad, during a normal operation of the memory device, and
- the DDR test controller generates the internal data strobe signal based on the first signal received through the first pad in at least a portion of the DDR test operation of the memory device.
4 more elements
Dependencies are inferred from the claim text.