Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsTakeshi HIOKA, Tsukasa KOBAYASHI, Koji KATO, Yuki SHIMIZU, Hiroshi MAEJIMA
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Abstract
According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.
Claims20
A semiconductor memory device comprising:
- first and second memory cells;
- a first word line connected to the first and second memory cells;
- a first bit line connected to the first memory cell;
- a second bit line connected to the second memory cell;
- a first sense amplifier connected to the first bit line, the first sense amplifier having a first node to determine data;
- a second sense amplifier connected to the second bit line, the second sense amplifier having a second node to determine data;
- and
- a voltage generation circuit,
- wherein in a read operation,
- the first node of the first sense amplifier is charged to a first voltage by the voltage generation circuit and is then connected to the first bit line, and
- the second node of the second sense amplifier is charged to a second voltage different from the first voltage by the voltage generation circuit and is then connected to the second bit line.
A semiconductor memory device comprising:
- first and second memory cells;
- a first word line connected to the first and second memory cells;
- a first bit line connected to the first memory cell;
- a second bit line connected to the second memory cell;
- a first sense amplifier connected to the first bit line, the first sense amplifier having a first node to determine data;
- a second sense amplifier connected to the second bit line, the second sense amplifier having a second node to determine data;
- and
- a control circuit which supplies control signals to the first sense amplifier and the second sense amplifier,
- wherein in a read operation,
- the control circuit supplies a first control signal to connect the first node of the first sense amplifier to the first bit line, and a second control signal to connect the second node of the second sense amplifier to the second bit line, and
- a timing at which supply of the first control signal ends and a timing at which supply of the second control signal ends are different.
Dependencies are inferred from the claim text.