Back to results
US 2022/0012580 A1Published application
Power-efficient compute-in-memory pooling
AssigneeQUALCOMM Incorporated
InventorAnkit SRIVASTAVA
Life of this patent
Estimating the term…
Abstract
A multiply-and-accumulate (MAC) circuit having a plurality of compute-in-memory bitcells is configured to multiply a plurality of stored weight bits with a plurality of input bits to provide a MAC output voltage. A successive approximation analog-to-digital converter includes a capacitive-digital-to-analog-converter (CDAC) configured to subtract a bias voltage from the MAC output voltage to provide a CDAC output voltage. A comparator compares the CDAC output voltage to a fixed reference voltage.
Claims25
A system for a machine learning application, comprising:
- a first multiply-and-accumulate (MAC) circuit including a first plurality of compute-in-memory bitcells configured to multiply a first plurality of stored weights with an input vector to provide a first MAC output voltage;
- and
- an analog-to-digital converter configured to digitize the first MAC output voltage, the analog-to-digital converter including:
- a first capacitive digital-to-analog converter (CDAC) configured to subtract a bias voltage from the first MAC output voltage to provide a first CDAC output voltage;
- and
- a first comparator configured to compare the first CDAC output voltage to a reference voltage to provide a first comparator output signal.
3 more elements
A system for a machine learning application, comprising:
- a first multiply-and-accumulate (MAC) circuit including a first plurality of compute-in-memory bitcells configured to multiply a first plurality of stored weights with an input vector to provide a first MAC output voltage;
- a second MAC circuit including a second plurality of compute-in-memory bitcells configured to multiply a second plurality of stored weights with the input vector to provide a second MAC output voltage;
- and
- an analog-to-digital converter configured to digitize either the first MAC output voltage or the second MAC output voltage, the analog-to-digital converter including:
- a first sampling switch;
- a second sampling switch;
- a first capacitive digital-to-analog converter (CDAC) configured to sample the first MAC output voltage through the first sampling switch to provide a sampled first MAC output voltage and to subtract a first bias voltage from the sampled first MAC output voltage to provide a first CDAC output voltage;
- a second capacitive digital-to-analog converter (CDAC) configured to sample the second MAC output voltage through the second sampling switch to provide a sampled second MAC output voltage and to subtract a second bias voltage from the sampled second MAC output voltage to provide a second CDAC output voltage;
- and
- a comparator configured to assert a comparator output signal responsive to the first CDAC output voltage being greater than the second CDAC output voltage.
7 more elements
A system for a machine learning application, comprising:
- a multiply-and-accumulate (MAC) circuit including a plurality of compute-in-memory bitcells configured to multiply a plurality of stored weights with a first input vector to provide a first MAC output voltage and to multiply the plurality of stored weights with a second input vector to provide a second MAC output voltage;
- and
- an analog-to-digital converter configured to digitize either the first MAC output voltage or the second MAC output voltage, the analog-to-digital converter including:
- a capacitive digital-to-analog converter (CDAC) configured to subtract a bias voltage from the first MAC output voltage to provide a first CDAC output voltage and to subtract the bias voltage from the second MAC output voltage to provide a second CDAC output voltage;
- a comparator configured to compare the first CDAC output voltage to a reference voltage to provide a first comparator output signal responsive to a first assertion of a local enable signal;
- and
- a logic gate configured to perform a second assertion of the local enable signal responsive to the first comparator output signal being false, wherein the comparator is further configured to compare the second CDAC output voltage to the reference voltage to provide a second comparator output signal responsive to the second assertion of the local enable signal.
4 more elements
A system for a machine learning application, comprising:
- a multiply-and-accumulate (MAC) circuit including a plurality of compute-in-memory bitcells configured to multiply a plurality of stored weights with a first input vector to provide a first MAC output voltage and to multiply the plurality of stored weights with a second input vector to provide a second MAC output voltage;
- and
- an analog-to-digital converter configured to digitize either the first MAC output voltage or the second MAC output voltage, the analog-to-digital converter including:
- a first sampling switch;
- a second sampling switch;
- a first capacitive digital-to-analog converter (CDAC) configured to sample the first MAC output voltage through the first sampling switch to provide a sampled first MAC output voltage;
- and
- a second capacitive digital-to-analog converter (CDAC) configured to sample the second MAC output voltage through the second sampling switch to provide a sampled second MAC output voltage;
- an averaging switch coupled between the first CDAC and the second CDAC, wherein the averaging switch is configured to close to average the sampled first MAC output voltage with the sampled second MAC output voltage to provide an averaged MAC output voltage;
- and
- a comparator configured to compare the averaged MAC output voltage to a reference voltage to provide a comparator output signal.
8 more elements
Dependencies are inferred from the claim text.