Mixed Poly Pitch Design Solution for Power Trim

A method of integrated circuit layout design optimization using mixed poly pitch cells for manufacturing integrated circuit, the method comprising:

• deploying an integrated circuit layout with mixed poly pitch cells, wherein the integrated circuit layout comprises:
• a number of minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, wherein both the first number and the second number are integers larger than 1;
• wherein the first pitch size PP is different from the second pitch size PP1,
• wherein the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1;
• wherein a gate length of the first pitch size is Lg;
• wherein a gate length of the second pitch size is Lg1;
• defining a plurality of equivalent cell types no greater than each of the number of minimum unit;
• optimizing the integrated circuit layout design by optimizing each of the minimum unit, wherein optimizing each of the minimum unit further comprises:
• selecting one of the plurality of the equivalent cell types with a pitch size combination and a gate length combination which optimizes a speed and a total power of the integrated circuit;
• and
• manufacturing the integrated circuit with the optimized integrated circuit layout deign.

An integrated circuit layout with mixed poly pitch cells with a plurality of different pitch sizes, the integrated circuit layout comprising:

• a plurality of minimum units each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size,
• wherein the first pitch size PP is different from the second pitch size PP1,
• wherein a gate length of the first pitch size is Lg;
• wherein a gate length of the second pitch size is Lg1;
• and
• wherein the layout is formed based on a modification of an initial layout, wherein the modification comprises increasing a length of one of Lg and Lg1 by a gate parameter modification magnitude selected to achieve G-bias of the minimum unit.