Systems and Methods for Generating Synthesizable Netlists From Register Transfer Level Designs

A system for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design comprising:

• a configuration tracer for generating size information associated with at least a portion of an RTL design corresponding to the semiconductor device;
• a register compiler for compiling a set of semiconductor devices based on power, performance, and area (PPA) information across a plurality of technology sizes, each technology size have different module sizes;
• a PPA-profiler for identifying semiconductor devices within the set of semiconductor devices generated by a register compiler that meet predefined PPA conditions by querying the PPA information across the plurality of technology sizes and the different module sizes;
• and
• a technology options configurator for creating a set of one or more synthesizable semiconductor device configurations based on user defined parameters such that one of the synthesizable semiconductor device designs can be selected to generate a design netlist based on the size information and the compiled set of semiconductor devices.

A system for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design comprising:

• an automatic-RTL configuration tracer for generating behavior information associated with at least a portion of an RTL design corresponding to one or more memory devices associated with the semiconductor device;
• a memory register compiler for compiling a set of memory devices based on one or more technologies and power, performance, and area (PPA) information across a plurality of technology sizes, each technology size have different module sizes;
• a PPA-aware profiler for identifying memory devices within the set of memory devices generated by the memory register compiler that meet predefined power, performance, and area conditions by querying the PPA information across the plurality of technology sizes and the different module sizes;
• a memory wrapper for generating structural information for aligning the input/output ports of the memory device;
• and
• a technology options configurator for creating a set of one or more synthesizable memory device configurations based on user defined parameters such that one of the synthesizable memory device designs can be selected to generate a design netlist with structure-synthesizable input/output boundary compatible memory device modules.