Object and cacheline granularity cryptographic memory integrity
AssigneeIntel Corporation
InventorsDavid M. Durham, Michael LeMay, Santosh Ghosh, Sergej Deutsch
Life of this patent
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AssigneeIntel Corporation
InventorsDavid M. Durham, Michael LeMay, Santosh Ghosh, Sergej Deutsch
Estimating the term…
Technologies disclosed herein provide one example of a system that includes processor circuitry and integrity circuitry. The processor circuitry is to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation of memory circuitry. The integrity circuitry is to determine a location of a metadata region within a cacheline that includes at least some of the address range, identify a first portion of the cacheline based at least in part on a first data bounds value stored in the metadata region, generate a first integrity value based on the first portion of the cacheline, and prevent the memory access operation in response to determining that the first integrity value does not correspond to a second integrity value stored in the metadata region.
A system, comprising:
A machine-readable storage medium including instructions that, when executed by one or more processors, causes the one or more processors to:
A method comprising:
A processor, comprising circuitry to:
Dependencies are inferred from the claim text.