Apparatus and method for multithreading-aware performance monitoring events

A processor comprising:

• a plurality of performance monitor counters, each performance monitor counter to count baseline events during processing of a plurality of instruction threads by a simultaneous multithreading (SMT) core;
• and
• a performance monitor unit to determine, for each instruction thread of the plurality of instruction threads, a number of core cycles in which the instruction thread is active and generating a first baseline event, wherein when two or more instruction threads of the plurality of instruction threads are concurrently active and generating the first baseline event in a given core cycle, a count of the first baseline event in the given core cycle is recorded only for one of the two or more instruction threads.

A method comprising:

• counting, via a plurality of performance monitor counters, baseline events during processing of a plurality of instruction threads a simultaneous multithreading (SMT) core;
• and
• determining, for each instruction thread of the plurality of instruction threads, a number of core cycles in which the instruction thread is active and generating a first baseline event, wherein when two or more instruction threads of the plurality of instruction threads are concurrently active and generating the first baseline event in a given core cycle, a count of the first baseline event in the given core cycle is recorded only for one of the two or more instruction threads.

A apparatus comprising:

• first counting means for counting baseline events with a plurality of performance monitor counters during processing of a plurality of instruction threads by a simultaneous multithreading (SMT) core;
• and
• second counting means for determining, for each instruction thread of the plurality of instruction threads, a number of core cycles in which the instruction thread is active and generating a first baseline event, wherein when two or more instruction threads of the plurality of instruction threads are concurrently active and generating the first baseline event in a given core cycle, a count of the first baseline event in the given core cycle is recorded only for one of the two or more instruction threads.