Systems and Methods for Sparsity Operations in a Specialized Processing Block

An integrated circuit device comprising a digital signal processing (DSP) block, wherein the DSP block comprises:

• a fracturable column comprising:
• a plurality of weight registers configurable to receive and store a first plurality of values;
• a plurality of multipliers, wherein each respective multiplier of the plurality of multipliers is configurable to receive a respective value of the first plurality of values;
• one or more inputs configurable to receive a second plurality of values;
• a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the plurality of multipliers, wherein the plurality of multipliers is configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products;
• and
• first adder circuitry configurable to generate a first sum from a first portion of the plurality products and generate a second sum from a second portion of the plurality of products;
• and
• input circuitry configurable to receive a first value and a second value from a second DSP block;
• second adder circuitry configurable to:
• receive the first sum and the first value and generate a third sum by adding the first sum and the first value;
• receive the second sum and the second value and generate a fourth sum by adding the second sum and the second value;
• and
• output circuitry configurable to output the third sum and the fourth sum from the DSP block to a third DSP block.

A digital signal processing (DSP) block comprising:

• a first fracturable column comprising:
• a plurality of weight registers configurable to receive and store a first plurality of values;
• a plurality of multipliers, wherein each respective multiplier of the plurality of multipliers is configurable to receive a respective value of the first plurality of values;
• one or more inputs configurable to receive a second plurality of values;
• a plurality of control registers configurable to store a third plurality of values, wherein:
• a multiplexer network is configurable to:
• receive the second plurality of values and the third plurality of values;
• and
• route each respective value of the second plurality of values to a multiplier of the plurality of multipliers based on the third plurality of values, wherein the plurality of multipliers is configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products;
• and
• first adder circuitry configurable to generate a first sum from a first portion of the plurality products and generate a second sum from a second portion of the plurality of products;
• and
• input circuitry configurable to receive a first value and a second value from a second DSP block;
• second adder circuitry configurable to:
• receive the first sum and the first value and generate a third sum by adding the first sum and the first value;
• receive the second sum and the second value and generate a fourth sum by adding the second sum and the second value;
• and
• output circuitry configurable to output the third sum and the fourth sum from the DSP block to a third DSP block.