Parallel Memory Access and Computation in Memory Devices

A method implemented in an integrated circuit memory device, the method comprising:

• storing a plurality of lists of operands in a plurality of first memory regions of the integrated circuit memory device;
• receiving, in a communication interface of the integrated circuit memory device, a first request;
• in response to the first request,
• accessing, by an arithmetic compute element matrix of the integrated circuit memory device, the plurality of first memory regions in parallel;
• computing, by the arithmetic compute element matrix, a list of results from the plurality of lists of operands stored in the plurality of first memory regions;
• and
• storing, into a second memory region of the integrated circuit memory device, the list of results;
• during a time period after the first request and before completion of the storing of the list of results into the second memory region, receiving, in the communication interface, a second request to access a third memory region in the plurality of memory regions;
• and
• in response to the second request and during the time period, providing, in parallel and by the integrated circuit memory device, memory access to the first memory regions and the second memory region to the arithmetic compute element matrix in facilitating the computation of the list of results and memory access to the third memory region to service the second request through the communication interface.

A computing apparatus, comprising:

• a processing device;
• a memory device encapsulated within an integrated circuit package;
• and
• a communication connection between the memory device and the processing device;
• wherein the memory device comprises:
• a plurality of memory regions;
• an arithmetic compute element matrix coupled to access the plurality of memory regions in parallel;
• and
• a communication interface coupled to the arithmetic compute element matrix and configured to receive a first request from the processing device through the communication connection;
• wherein, in response to the first request, the arithmetic compute element matrix is configured to access a plurality of lists of operands stored in first memory regions in the plurality of memory regions, generate a list of results from the plurality of lists of operands, and store the list of results in a second memory region in the plurality of memory regions;
• wherein, during a time period after the first request and before completion of storing the list of results into the second memory region, the communication interface is configured to receive from the processing device, a second request to access a third memory region in the plurality of memory regions;
• and
• wherein, in response to the second request and during the time period, the memory device is configured to provide, in parallel, memory access to the first memory regions and the second memory region to the arithmetic compute element matrix in facilitating the computation of the list of results and memory access to the third memory region to service the second request through the communication interface.