Methods and apparatus to control an aggressiveness of display panel power savings and fidelity

An apparatus comprising:

• a display panel;
• a display controller to adjust an image to be displayed by the display panel;
• and
• processor circuitry including one or more of:
• at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus;
• a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations;
• or
• Application Specific Integrate Circuitry (ASIC) including logic gate circuitry to perform one or more third operations;
• the processor circuitry to perform at least one of the first operations, the second operations or the third operations to instantiate:
• image accessor circuitry to access an image provided to the display controller;
• model executor circuitry to execute a machine learning model using the image as an input to generate an aggressiveness value;
• and
• aggressiveness provider circuitry to provide the aggressiveness value to the display controller, the display controller to adjust the image based on the aggressiveness value prior to display of the adjusted image by the display panel.