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AssigneeThe George Washington University
InventorsHao ZHENG, Ke WANG, Ahmed LOURI
Estimating the term…
An interconnection network for a processing unit having an array of cores. The interconnection network includes routers and adaptable links that selectively connect routers in the interconnection network. For example, each router may be electrically connected to one or more of the adaptable links via one or more multiplexers and a link controller may control the multiplexers to selectively connect routers via the adaptable links. In another example, adaptable links may be formed as part of an interposer and the link controller selectively connect routers via the adaptable links in the interposer using interposer switches. The adaptable links enable the interconnection network to be dynamically partitioned. Each of those partitions may be dynamically reconfigured to form a topology.
An on-chip interconnection network for a processing unit having an array of cores, the interconnection network comprising:
A method of dynamically reconfiguring an interconnection network that includes an array of routers, the method comprising:
Dependencies are inferred from the claim text.