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US 2021/0344616 A1Published application
Use of stashing buffers to improve the efficiency of crossbar switches
AssigneeNVIDIA Corporation
InventorsMatthias Augustin Blumrich, Nan Jiang, Larry Robert Dennison
Life of this patent
Estimating the term…
Abstract
A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.
Claims23
1-21. (canceled)
A switch comprising:
- a plurality of input ports receiving packets into an input port buffer;
- a plurality of output ports receiving packets from an output port buffer;
- a stash partition comprising memory addresses allocated from both of the input port buffer and the output port buffer;
- a switching fabric interposed between the input port buffer and the output port buffer;
- and
- a packet path from the stash partition through the switching fabric and back to the stash partition, the packet path bypassing the input ports and the output ports.
3 more elements
A switch comprising:
- a first switch fabric coupling a plurality of packet sources to a plurality of packet destinations;
- and
- a second switch fabric also coupling the plurality of packet sources to the plurality of packet destinations;
- and
- a stash partition coupled to the first switch fabric and to the second switch fabric, the stash partition comprising memory addresses from both of input buffers and output buffers of the switch;
- and
- logic to:
- store, in the stash partition, packets that pass from the packet sources to the packet destinations through the second switch fabric;
- and
- recirculate the packets through the first switch fabric from the stash partition to the packet destinations.
7 more elements
A switch comprising:
- a plurality of input ports;
- a plurality of output ports;
- a switching fabric ;
- a buffer memory coupled to both of the input ports and the output ports and comprising:
- a first memory allocation for a buffer partition, and
- a second memory allocation for a stash partition, the stash partition coupled to recirculate packets received at the input ports through the switching fabric while bypassing the input ports and output ports;
- and
- memory management logic configured to control the allocations of the buffer partition and the stash partition.
5 more elements
The switch of claim 1, the stash partition comprising memory addresses from both of an input port buffer and an output port buffer.
A switch comprising:
- a switching fabric to route packets received at input ports of the switch to output ports of the switch;
- an input buffer to store the packets received at the input ports prior to routing the packets through the switching fabric;
- an output buffer to store packets routed through the switching fabric prior to outputting the packets from the output ports;
- a stash partition formed from both of the input buffer and the output buffer;
- and
- wherein the input buffer, the output buffer, and the stash partition form a path that bypasses the input ports and the output ports to recirculate packets within the switch.
3 more elements
Dependencies are inferred from the claim text.