Processing-in-memory (pim) devices

A processing-in-memory (PIM) device comprising:

• a storage region configured to receive and store first write data, a first write fail check signal, second write data, and a second write fail check signal when a write operation in an operation mode is performed, and output first read data, a first read fail check signal, second read data, and a second read fail check signal when a read operation in the operation mode is performed;
• and
• a cyclic redundancy checking (CRC) logic circuit configured to generate the first write data, the first write fail check signal, the second write data, and the second write fail check signal from first write input data and second write input data when the write operation in the operation mode is performed, and generate first converted data and second converted data from the first read data, the first read fail check signal, the second read data, and the second read fail check signal when the read operation in the operation mode is performed.