Processing-in-memory (pim) devices
AssigneeSK hynix Inc.
InventorChoung Ki SONG
Life of this patent
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Abstract
A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate first write data, first write parity, second write data, and second write parity from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data and second converted data from first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data to generate MAC operation result data.
Claims25
A processing-in-memory (PIM) device comprising:
- an error correction code (ECC) logic circuit configured to generate first write data, first write parity, second write data, and second write parity from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data and second converted data from first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed;
- and
- a multiplication and accumulation (MAC) operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data to generate MAC operation result data.
A processing-in-memory (PIM) device comprising:
- a storage region configured to receive and store first write data, first write parity, second write data, and second write parity when a write operation in an operation mode is performed, and output first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed;
- and
- an error correction code (ECC) logic circuit configured to generate the first write data, the first write parity, the second write data, and the second write parity from first write input data and second write input data when the write operation in the operation mode is performed, and generate first converted data and second converted data from the first read data, the first read parity, the second read data, and the second read parity when the read operation in the operation mode is performed.
Dependencies are inferred from the claim text.