Phy-based retry techniques for die-to-die interfaces

A system comprising:

• a first die;
• a second die;
• and
• a die-to-die-interface to couple the first die and the second die;
• wherein the first die comprises a first interface controller and first PHY circuitry, the first PHY circuitry comprising:
• a retry buffer;
• error detection code generation circuitry;
• wherein the first PHY circuitry is to transmit data from the first interface controller and error correction codes corresponding to the data generated by the error detection code generation circuitry;
• the second die comprises a second interface controller and second PHY circuitry, the second PHY circuitry comprising:
• error detection circuitry to detect errors in the data transmitted by the first PHY circuitry based on the error detection codes;
• and
• based on detection of an error in the data, assert a stall signal to the first PHY circuitry and block the data from being passed to the second interface controller;
• and
• the first PHY circuitry is further to:
• detect the stall signal asserted by the second PHY circuitry;
• and
• based on detecting the asserted stall signal, transmit retry data from the retry buffer and error correction codes corresponding to the retry data generated by the error detection code generation circuitry.

A method comprising:

• filling, by first physical layer (PHY) circuitry, a retry buffer with data from an interface controller;
• generating, by the first PHY circuitry, error detection codes based on the data;
• transmitting the data and corresponding error correction codes to second PHY circuitry;
• detecting, at the first PHY circuitry, a stall signal asserted by the second PHY circuitry;
• generating, by the first PHY circuitry, error detection codes for the data in the retry buffer;
• and
• transmitting the data from the retry buffer and its corresponding error detection codes to the second PHY circuitry.

A method comprising:

• receiving, at second physical layer (PHY) circuitry, data and error correction codes corresponding to the data from first PHY circuitry;
• detecting, by the second PHY circuitry, an error in the data based on the error correction codes;
• blocking, by the second PHY circuitry, the data from being passed to an interface controller for processing based on the detected error;
• and
• asserting, by the second PHY circuitry, a stall signal to the first PHY circuitry based on the detected error.