Memory controller and method of data bus inversion using an error detection correction code

A memory module, comprising:

• a substrate;
• multiple memory devices disposed on the substrate;
• a multi-bit data interface including multiple data pins defining a multi-bit width;
• the multiple memory devices to receive write data bits from a memory controller via the multi-bit data interface, the write data bits selectively inverted by the memory controller in accordance with a Data Bus Inversion (DBI) coding scheme;
• the multiple memory devices to store the selectively inverted write data bits;
• and
• the multiple memory devices to transmit the selectively inverted write data bits as read data to the memory controller via the multiple data pins in response to a read command, the read data unaccompanied by a control signal from the memory module to indicate whether the read data is DBI-encoded.

A method of operation in a memory module, the memory module including multiple memory devices disposed on a substrate, the method comprising:

• receiving, at the memory module, write data bits from a memory controller, the write data bits received as selectively inverted by the memory controller in accordance with a Data Bus Inversion (DBI) coding scheme;
• storing, in each of the multiple memory devices, respective portions of the selectively inverted write data bits;
• and
• transmitting, from each of the multiple memory devices, the respective portions of the selectively inverted write data bits as read data to the memory controller in response to a read command, the read data unaccompanied by a control signal from the memory module to indicate whether the read data is DBI-encoded.

A dynamic random access memory (DRAM) memory module comprising:

• a substrate;
• multiple DRAM integrated circuit (IC) memory devices disposed on the substrate;
• a multi-bit data interface including multiple data pins defining a multi-bit width;
• the multiple memory devices to receive write data bits from a DRAM IC memory controller via the multi-bit data interface, the write data bits selectively inverted by the DRAM IC memory controller in accordance with a Data Bus Inversion (DBI) coding scheme;
• the multiple DRAM IC memory devices to store the selectively inverted write data bits;
• and
• the multiple DRAM IC memory devices to transmit the selectively inverted write data bits as read data to the DRAM IC memory controller via the multiple data pins in response to a read command, the read data unaccompanied by a control signal from the memory module to indicate whether the read data is DBI-encoded.