US 2021/0344348 A1 · SELF-TUNING PHASE-LOCKED LOOP (PLL) CIRCUIT

Abstract

Embodiments may relate to techniques or circuitry for the control of a clock signal by a phase-locked loop (PLL) circuit. The technique may include the identification of a first parameter related to a gain of a digitally controlled oscillator (DCO) and a second parameter related to a resolution of a time-to-digital converter (TDC). The technique may then include the identification of a third parameter related to filter coefficients of a loop filter of the PLL circuit based on the first and second parameter. The circuit may then output a clock signal based on the first, second, and third parameters. Other embodiments may be described or claimed.

Claims25

Dependent claims

A method of controlling a clock signal by a phase-locked loop (PLL) circuit, wherein the method comprises:

identifying, by the PLL circuit, a first parameter related to a gain of a digitally controlled oscillator (DCO) of the PLL circuit;
identifying, by the PLL circuit, a second parameter related to a resolution of a time-to-digital converter (TDC) of the PLL circuit;
setting coefficients of a loop filter of the PLL circuit to modify a loop gain of the PLL circuit based on the first parameter and the second parameter;
and
outputting, by the PLL circuit, the clock signal, where the clock signal is based on the coefficients of the loop filter.

2 more elements

Dependencies are inferred from the claim text.

Self-tuning phase-locked loop (pll) circuit

Life of this patent

Self-tuning phase-locked loop (pll) circuit

Life of this patent

Abstract

Claims25