Back to results
US 2021/0344346 A1Published application
Integrated circuit including back side conductive lines for clock signals
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKam-Tou SIO, Jiun-Wei LU
Life of this patent
Estimating the term…
Abstract
An integrated circuit is disclosed, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.
Claims20
An integrated circuit, comprising:
- a first latch circuit and a second latch circuit, wherein the first latch circuit is configured to transmit a plurality of data signals to the second latch circuit through a plurality of first conductive lines disposed on a front side of the integrated circuit;
- and
- a clock circuit configured to transmit a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through a plurality of second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.
An integrated circuit, comprising:
- a flip flop circuit including a first cell having a first cell height and a second cell having a second cell height, and comprising:
- a first transistor in the first cell, comprising:
- a first gate configured to receive a first signal from a first conductive line disposed on a front side of the integrated circuit;
- and
- a first active region configured to transmit a first clock signal, according to the first signal, to a second conductive line in a first layer on a back side, opposite to the front side, of the integrated circuit;
- a third conductive line disposed in a second layer, below the first layer, on the back side of the integrated circuit and coupled to the second conductive line;
- and
- a second transistor in the second cell, comprising:
- a second gate configured to receive the first clock signal through a fourth conductive line which is disposed in the first layer on the back side of the integrated circuit and coupled to the third conductive line;
- and
- a second active region configured to transmit a second clock signal, according to the first clock signal, to a fifth conductive line in the first layer on the back side of the integrated circuit, wherein the second clock signal is generated by inverting the first clock signal.
8 more elements
A method, comprising:
- forming an active device operating as a scan flip flop circuit on a front side of an integrated circuit;
- forming a plurality of first conductive lines extending in a first direction in a first layer on a back side of the integrated circuit to transmit a first clock signal and a second clock signal to the active device;
- forming a plurality of second conductive lines in the first layer on the back side of the integrated circuit to transmit a first supply voltage and a second supply voltage to the active device, wherein the plurality of first conductive lines are interposed between the plurality of second conductive lines;
- forming a plurality of third conductive lines extending in a second direction different from the first direction in a second layer on the back side of the integrated circuit to transmit the first clock signal and the second clock signal between the plurality of first conductive lines, wherein the first layer is disposed between the second layer and the front side of the integrated circuit;
- and
- forming a plurality of fourth conductive lines extending parallel to the plurality of third conductive lines in the second layer on the back side of the integrated circuit to transmit the first supply voltage and the second supply voltage to the plurality of second conductive lines, wherein the plurality of third conductive lines are interposed between the plurality of fourth conductive lines.
3 more elements
Dependencies are inferred from the claim text.