Input circuit

An input circuit that receives an input signal at an input terminal, the input circuit comprising:

• an input buffer circuit using a first node as an input and a second node as an output;
• an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a power supply;
• and
• a pull-up circuit provided between the first node and the power supply,
• wherein
• the pull-up circuit includes first and second P-type transistors coupled in series between the power supply and the first node,
• the first P-type transistor receives an inversion signal of a signal of the first node at a gate thereof, and
• the second P-type transistor receives a signal of the second node at a gate thereof when the input buffer circuit is a buffer that does not invert a logic of a signal and receives an inversion signal of the signal of the second node at the gate when the input buffer circuit is an inverter.

An input circuit that receives an input signal at an input terminal, the input circuit comprising:

• an input buffer circuit using a first node as an input and a second node as an output;
• an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a third node;
• a pull-up circuit provided between the first node and the third node;
• and
• a voltage conversion circuit configured to output a voltage of a power supply to the third node when the power supply is on and divide a voltage of the input terminal to output the divided voltage to the third node when the power supply is off,
• wherein
• the pull-up circuit is configured, while the power supply is on, to make the third node and the first node conductive with each other for a predetermined period when the input signal transitions from low to high, and not to make the third node and the first node conductive with each other when the input signal transitions from high to low.

An input circuit that receives an input signal at an input terminal, the input circuit comprising:

• an input buffer circuit using a first node as an input and a second node as an output;
• an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a third node;
• a pull-up circuit provided between the first node and the third node;
• and
• a voltage conversion circuit configured to output a voltage of a power supply to the third node when the power supply is on and divide a voltage of the input terminal to output the divided voltage to the third node when the power supply is off,
• wherein
• the pull-up circuit includes first and second P-type transistors coupled in series between the third node and the first node,
• the first P-type transistor receives an inversion signal of the signal of the first node at a gate thereof, and
• the second P-type transistor receives the signal of the second node at a gate thereof when the input buffer circuit is a buffer that does not invert a logic of a signal and receives an inversion signal of the signal of the second node at the gate when the input buffer circuit is an inverter.