Level shifter enable
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorSrinivasan Ramarajan
Life of this patent
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Abstract
A multi-bit level shifter that has a plurality of level shifters, each of which is configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain. The level shifters each have an enable node. An enable circuit includes an output terminal connected to the enable node of each of the plurality of level shifters, and each of the plurality of level shifters is configured to output the corresponding output signals in response an enable signal received by the enable circuit.
Claims20
A level shifter enable circuit, comprising:
- an inverter configured to receive a first power supply voltage and having an input terminal and an output terminal;
- a plurality of first control transistors, each of the first control transistors having a source connected to a ground terminal, a gate connected to the output terminal of the inverter, and a drain connected to a respective one of a plurality of level shifters;
- a plurality of second control transistors, each of the second control transistors having a source connected to the ground terminal, a gate connected to the output terminal of the inverter, and a drain connected to the respective one of the plurality of level shifters;
- and
- a third control transistor having a source configured to receive the first power supply voltage, a gate connected to the output terminal of the inverter, and a drain connected to an inverter of each of the plurality of level shifters.
A system, comprising:
- a plurality of level shifters, each configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain, each of the plurality of level shifters including an enable node;
- and
- an enable circuit having an output terminal connected to the enable node of each of the plurality of level shifters, the enable circuit configured to receive a first enable signal and output a second enable signal to the enable node of each of the plurality of level shifters, wherein each of the plurality of level shifters is configured to output the corresponding output signal in response to the second enable signal output by the enable circuit;
- a data bus having a plurality of data lines, each of the data lines connected to provide the input signal in the first voltage domain to a respective one of the plurality of level shifters;
- and
- a logic circuit configured to receive the output signals in the second voltage domain from the plurality of level shifters.
A device, comprising:
- an inverter configured to receive a first power supply voltage and having an input terminal and an output terminal;
- a plurality of first control transistors connectable between a respective one of a plurality of level shifters and a ground terminal, each of the first control transistors having a gate connected to the output terminal of the inverter;
- and
- a plurality of second control transistors connectable between a respective one of the plurality of level shifters and the ground terminal, each of the second control transistors having a gate connected to the output terminal of the inverter.
Dependencies are inferred from the claim text.