Low Voltage Clock Swing Tolerant Sequential Circuits for Dynamic Power Savings

A circuit comprising:

• a pair of cross-coupled inverters enabled by a pair of pull-up transistors, wherein sources of the pair of pull-up transistors are coupled to a supply voltage at a first voltage level;
• one or more clock-gated P-type transistors coupled between drains of the pair of pull-up transistors, wherein gates of the one or more clock-gated P-type transistors are coupled to a clock signal, wherein a clock logic high level is equal to a second voltage level less than the first voltage level;
• and
• a pair of clock-gated N-type transistors coupled in parallel to state nodes of the pair of cross-coupled inverters.

A method comprising:

• supplying a pair of pull-up transistors with a supply voltage at a first voltage level;
• enabling, by the pair of pull-up transistors, a pair of cross-coupled inverters;
• receiving a clock signal at gates of one or more clock-gated P-type transistors coupled between drains of the pair of pull-up transistors, wherein a clock logic high level is equal to a second voltage level less than the first voltage level;
• and
• receiving the clock signal at gates of a pair of clock-gated N-type transistors coupled in parallel to state nodes of the pair of cross-coupled inverters.

A system comprising:

• a clock generator circuit;
• and
• logic circuitry comprising:
• a pair of cross-coupled inverters enabled by a pair of pull-up transistors, wherein sources of the pair of pull-up transistors are coupled to a supply voltage at a first voltage level;
• one or more clock-gated P-type transistors coupled between drains of the pair of pull-up transistors, wherein gates of the one or more clock-gated P-type transistors are coupled to a clock signal, wherein a clock logic high level is equal to a second voltage level less than the first voltage level;
• and
• a pair of clock-gated N-type transistors coupled in parallel to state nodes of the pair of cross-coupled inverters.