Ultra-low-power mode control circuit for power converter

An ultra-low-power mode control circuit for a power converter, comprising:

• a first P-channel metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first N-channel metal oxide semiconductor (NMOS) transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first capacitor, a second capacitor, a first inverter and a second inverter;
• wherein
• a source of the first PMOS transistor is connected to a high-voltage power source, a gate of the first PMOS transistor is connected to a drain of the second PMOS transistor, and a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor;
• a gate of the first NMOS transistor is connected to a mode selection switch, and a source of the first NMOS transistor is grounded;
• a source of the second PMOS transistor is connected to the high-voltage power source, and a gate of the second PMOS transistor is connected to the drain of the first PMOS transistor;
• a drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, a gate of the second NMOS transistor is connected to a drain of the fourth NMOS transistor, and a source of the second NMOS transistor is grounded;
• a gate of the fourth NMOS transistor is connected to the mode selection switch, and a source of the fourth NMOS transistor is grounded;
• a gate of the third NMOS transistor is grounded, a drain of the third NMOS transistor is connected to the mode selection switch, and a source of the third NMOS transistor is grounded;
• a positive terminal of the first capacitor is connected to the mode selection switch, and a negative terminal of the first capacitor is grounded;
• a positive terminal of the second capacitor is connected to the high-voltage power source, and a negative terminal of the second capacitor is connected to the drain of the fourth NMOS transistor;
• a source of the third PMOS transistor is connected to the high-voltage power source, a gate of the third PMOS transistor is connected to the high-voltage power source, and a drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor;
• a drain of the fifth NMOS transistor is connected to the drain of the second NMOS transistor, a gate of the fifth NMOS transistor is connected to a drain of the sixth NMOS transistor, and a source of the fifth NMOS transistor is grounded;
• a gate of the sixth NMOS transistor is connected to the mode selection switch, and a source of the sixth NMOS transistor is grounded;
• a drain of the fourth PMOS transistor is connected to the drain of the sixth NMOS transistor, a gate of the fourth PMOS transistor is connected to the mode selection switch, and a source of the fourth PMOS transistor is connected to a core voltage;
• an input of the first inverter is connected to the drain of the second PMOS transistor, and an output of the first inverter is connected to an external clock enable signal;
• and
• an input of the second inverter is connected to the drain of the first PMOS transistor, and an output of the second inverter is connected to a built-in clock enable signal.