Methods of manufacturing a field effect transistor using carbon nanotubes and field effect transistors
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTimothy VASEN, Marcus Johannes Henricus VAN DAL, Gerben DOOMBOS
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Abstract
In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.
Claims20
A method of forming a gate-all-around field effect transistor (“GAA FET”), the method comprising:
- forming a fin structure over a substrate, the fin structure including a plurality of carbon nanotubes each surrounded by a support layer;
- releasing channel regions of CNTs in the fin structure;
- forming a gate structure around the channel regions of the CNTs;
- releasing source/drain extension regions of the CNTs, the source/drain extension regions extending outward from the channel regions of the CNTs;
- forming an inner spacer structure surrounding the source/drain extension regions, the inner spacer structure including a first dielectric layer contacting the source/drain extension regions and a second dielectric layer over the first dielectric layer;
- and
- forming a source/drain structure adjacent to the source/drain extension regions and the inner spacer structure.
A structure, comprising:
- a substrate;
- a carbon nanotube over the substrate, the carbon nanotube including a channel portion and a source/drain extension portion extending from the channel portion;
- a gate structure wrapping around the channel portion of the carbon nanotube;
- an inner spacer structure wrapping around the source/drain extension portion of the carbon nanotube and adjacent to the gate structure, the inner spacer structure including a first dielectric layer contacting the source/drain extension portion and a second dielectric layer over the first dielectric layer;
- and
- a source/drain structure contacting the source/drain extension portion and laterally adjacent to the inner spacer structure.
An integrated circuit, comprising:
- a substrate;
- a plurality of carbon nanotubes over the substrate, the plurality of carbon nanotubes spaced away from one another in a vertical direction, the plurality of carbon nanotubes each including a channel portion and a source/drain extension portion extending from the channel portion;
- a gate structure surrounding channel portions of the plurality of carbon nanotube;
- a spacer structure surrounding source/drain extension portions of the plurality of carbon nanotubes, the spacer structure including a first dielectric layer contacting the source/drain extension portions and a second dielectric layer over the first dielectric layer;
- and
- a source/drain structure laterally adjacent to the spacer structure.
Dependencies are inferred from the claim text.