Semiconductor structure and method of manufacturing the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsFu-Ting SUNG, Chung-Chiang MIN, Yuan-Tai TSENG, Chern-Yow HSU, Shih-Chang LIU
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Abstract
The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.
Claims21
-20. (canceled)
A semiconductor structure, comprising:
- an Nth metal layer formed over a substrate;
- a bottom electrode over the Nth metal layer;
- a magnetic tunneling junction (MTJ) over the bottom electrode;
- a top electrode over the MTJ;
- and
- an (N+M)th metal layer over the Nth metal layer, N and M being nonzero, positive integers,
- wherein the (N+M)th metal layer extends from a first interface with the top electrode to a second interface with the top electrode, wherein the first interface is closer a top surface of the substrate than the second interface, wherein a dielectric material interfaces another portion of the top electrode below the first interface.
A semiconductor structure, comprising:
- a logic region;
- and
- a memory region, comprising:
- an Nth metal layer;
- a bottom electrode over the Nth metal layer;
- a magnetic tunneling junction (MTJ) over the bottom electrode;
- a top electrode over the MTJ;
- and
- an (N+1)th metal layer over the top electrode, N being a nonzero, positive integer;
- an isolation region adjacent the top electrode;
- and
- wherein the MTJ interfaces a bottom surface of the top electrode, the (N+1)th metal layer interfaces an uppermost surface of the top electrode and the (N+1)th metal layer interfaces a first region of a surface of the top electrode extending between the uppermost surface and the bottom surface of the top electrode;
- and
- the isolation region interfaces a second region of the surface of the top electrode, the second region below the first region.
A semiconductor structure, comprising:
- a semiconductor substrate having a memory region and a logic region;
- a first metal line of an Nth metal layer in the memory region and a second metal line of the Nth metal layer in the logic region;
- a bottom electrode over the first metal line of the Nth metal layer, the bottom electrode has a top surface;
- a magnetic tunneling junction (MTJ) over a first portion of the top surface of the bottom electrode;
- a dielectric layer over a second portion and a third portion of the top surface of the bottom electrode, wherein the first portion interposes the second and third portions of the top surface;
- a top electrode over the MTJ, the top electrode interfaces the dielectric layer;
- and
- a first metal line of an (N+1)th metal layer over the top electrode, N being a positive, nonzero integer,
- wherein a surface of the top electrode interfaces the (N+1)th metal layer from a first point to a second point, the second point higher than the first point.
Dependencies are inferred from the claim text.