Capacitor structure and semiconductor devices having the same
AssigneeSamsung Electronics Co., Ltd.
InventorsEUN-SUN KIM, SANG-YEOL KANG, KYOO-HO JUNG, KYU-HO CHO, HYO-SIK MUN
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Abstract
A capacitor includes a lower electrode including a first metal material and having a first crystal size in a range of a few nanometers, a dielectric layer covering the lower electrode and having a second crystal size that is a value of a crystal expansion ratio times the first crystal size and an upper electrode including a second metal material and covering the dielectric layer. The upper electrode has a third crystal size smaller than the second crystal size.
Claims20
A semiconductor device comprising:
- a substrate;
- and
- a plurality of memory cell structures arranged on the substrate and electrically connected to surroundings through a contact structure, a support, and a capacitor,
- wherein the capacitor includes:
- a lower electrode comprising a first metal material and having a crystal size of a few nanometers in such a configuration that the lower electrode is connected with the contact structure and supported by at least the support;
- a dielectric layer comprising dielectric material covering the first metal material, the dielectric material comprising merged crystals that each include a plurality of crystals, the merged crystals having a crystal size that is a value of a crystal expansion ratio times the crystal size of the first metal material, wherein the crystal expansion ratio is an integer;
- and
- an upper electrode covering the dielectric layer, the upper electrode comprising a second metal material and having a crystal size smaller than the crystal size of the dielectric material.
A semiconductor device comprising:
- a substrate;
- and
- a plurality of memory cell structures arranged on the substrate and electrically connected to surroundings through a contact structure, a support, and a capacitor,
- wherein the capacitor includes:
- a lower electrode comprising a layer of metal material having a crystal size in a range of 3-10 nanometers;
- a dielectric covering the layer of metal material of the lower electrode and comprising a layer of dielectric material, the dielectric material comprising merged crystals that each include a plurality of crystals, the merged crystals having a crystal size that is 5-20 times the crystal size of the layer of metal material of the lower electrode;
- and
- an upper electrode covering the dielectric, the upper electrode comprising a layer of metal material having a crystal size smaller than the crystal size of the layer of dielectric material.
A semiconductor device comprising:
- a substrate;
- a memory cell structure at an upper portion of the substrate;
- a lower insulation interlayer on the substrate and covering the memory cell structure;
- a plurality of lower wirings disposed in the lower insulation interlayer and electrically connected to the memory cell structure;
- an upper insulation interlayer on the plurality of the lower wirings;
- a plurality of upper wirings on the upper insulation interlayer;
- and
- a capacitor disposed on the lower insulation interlayer and covered by the upper insulation interlayer in such a configuration that the capacitor is electrically connected to the upper wirings,
- wherein the capacitor includes:
- a lower electrode comprising a layer of a metal material;
- a dielectric on the lower electrode and comprising a layer of dielectric material having a crystal size larger than a crystal size of the metal material of the lower electrode;
- and
- an upper electrode disposed on the dielectric and comprising a layer of metal material having a crystal size smaller than the crystal size of the layer of dielectric material.
Dependencies are inferred from the claim text.