Spacer-defined back-end transistor as memory selector

A memory device, comprising:

• a substrate;
• an interconnect structure disposed over the substrate, the interconnect structure comprising a plurality of interconnect metal layers one stacked over another and disposed in an interlayer dielectric (ILD) layer;
• a plurality of memory cells disposed within the interconnect structure and arranged in an array of rows and columns;
• and
• a plurality of selecting transistors correspondingly connected to the plurality of memory cells, wherein the plurality of selecting transistors is disposed within the interconnect structure between a lower interconnect metal layer and an upper interconnect metal layer of the interconnect structure.

A method of manufacturing a memory device, the method comprising:

• forming a lower interconnect metal layer over a substrate and surrounded by a lower interlayer dielectric (ILD) layer;
• forming a plurality of selecting transistors on the lower interconnect metal layer;
• forming an intermediate interconnect metal layer on the plurality of selecting transistors;
• forming a plurality of memory cells on the intermediate interconnect metal layer;
• and
• forming an upper interconnect metal layer on the plurality of memory cells.