US 2021/0343741 A1 · SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

A method of manufacturing a semiconductor device includes: forming a first patterned stack structure including a cell region, a first portion in a first contact region, and a second portion in a second contact region, the second portion of the first patterned stack structure including a first opening; forming a second patterned stack structure including a third portion over the cell region and the second contact region of the first patterned stack structure; forming a second opening penetrating the third portion of the second patterned stack structure, the second opening being coupled to the first opening; and forming a third opening penetrating the first portion of the first patterned stack structure when the second opening is formed.

Claims15

Dependent claims

A method of manufacturing a semiconductor device, the method comprising:

forming a first patterned stack structure including a cell region, a first portion in a first contact region, and a second portion in a second contact region, the second portion of the first patterned stack structure including a first opening;
forming a second patterned stack structure including a third portion over the cell region and the second contact region of the first patterned stack structure;
forming a second opening penetrating the third portion of the second patterned stack structure, the second opening being coupled to the first opening;
and
forming a third opening penetrating the first portion of the first patterned stack structure when the second opening is formed.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/373,409Filed 12 Jul 2021

Priority

KR 10-2019-001623412 Feb 2019

Published

4 Nov 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region

Semiconductor device and manufacturing method thereof

Life of this patent

Semiconductor device and manufacturing method thereof

Life of this patent

Abstract

Claims15