Electronic structures comprising multiple, adjoining high-k dielectric materials and related electronic devices, systems, and methods

An electronic structure comprising:

• stacks comprising conductive materials adjacent to one another and separated by air gaps, the stacks in a cell region of the electronic structure;
• a cell high-k dielectric material in the cell region and surrounding the conductive materials;
• a pillar high-k dielectric material adjacent to the stacks and adjoining a portion of the cell high-k dielectric material, the pillar high-k dielectric material in a pillar region of the electronic structure;
• and
• a charge blocking material, a nitride material, a tunnel dielectric material, and a channel material adjacent to the pillar high-k dielectric material and in the pillar region.

A method of forming an electronic device, comprising:

• forming stacks of alternating dielectric materials and nitride materials;
• forming a pillar high-k dielectric material adjacent to the alternating dielectric materials and nitride materials;
• forming a charge blocking material, a nitride material, a tunnel dielectric material, and a channel material adjacent to the pillar high-k dielectric material;
• forming an insulative material adjacent to the channel material;
• removing the nitride materials to form openings between the dielectric materials;
• and
• forming a cell high-k dielectric material in the openings, a portion of the cell high-k dielectric material adjoining a portion of the pillar high-k dielectric material;
• and
• forming a conductive material in the openings to form stacks of alternating dielectric materials and conductive materials.

An electronic device comprising:

• an array of memory cells, the memory cells comprising:
• stacks of alternating dielectric materials and conductive materials in a cell region of the electronic device;
• a pillar high-k dielectric material adjacent to the stacks and in a pillar region of the electronic device;
• an interlayer poly-dielectric structure and a channel material adjacent to the pillar high-k dielectric material;
• and
• a cell high-k dielectric material surrounding the conductive materials in the cell region, and a portion of the cell high-k dielectric material adjoining a portion of the pillar high-k dielectric material;
• and
• access lines and bit lines electrically coupled to the memory cells.

A system, comprising:

• a processor operably coupled to an input device and an output device;
• and
• an electronic device operably coupled to the processor, the electronic device comprising memory cells, one or more of the memory cells comprising:
• stacks of alternating dielectric materials and conductive materials in a cell region of the electronic device;
• a pillar high-k dielectric material, an interlayer poly-dielectric structure, and a channel material adjacent to the stacks and in a pillar region of the electronic device;
• and
• a cell high-k dielectric material in the cell region and a portion of the cell high-k dielectric material adjoining a portion of the pillar high-k dielectric material.