Method for improving control gate uniformity during manufacture of processors with embedded flash memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Han LIN, Wei Cheng WU
Life of this patent
Estimating the term…
Abstract
A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.
Claims20
A method, comprising:
- planarizing a protective layer over gate materials overlying a recessed region in a substrate, the planarizing including:
- forming a first planarized surface by planarizing a sacrificial layer over the protective layer;
- and
- forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region;
- forming an etch mask layer over the second planarized surface;
- and
- forming control gate stacks in the recessed region by etching the gate materials.
A method, comprising:
- forming a memory region surrounded by a processor region by recessing a first region of a substrate;
- forming a floating gate layer in the memory region;
- forming a control gate layer over the floating gate layer and extending to the processor region;
- forming a hard mask layer over the control gate layer;
- forming a sacrificial layer over the hard mask layer, the sacrificial layer having a first planar surface;
- forming a planarized surface of the hard mask layer by removing the sacrificial layer and the hard mask layer at substantially equal rates in an etch process;
- forming an etch mask layer over the hard mask layer to a substantially uniform thickness across the memory region;
- and
- forming gate stacks in the memory region having substantially uniform width by etching floating gate layer and the control gate layer under the etch mask layer.
A method, comprising:
- forming protective layer having a depression over a recessed region of a substrate;
- forming a self-leveling layer with a thickness that is sufficient to completely fill the depression;
- and
- forming a planarized surface on the protective layer by etching the self-leveling layer at an even rate across the recessed region to a depth sufficient to remove the sacrificial layer and a portion of the protective layer.
Dependencies are inferred from the claim text.