Semiconductor device and method of manufacturing the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsGuo-Huei WU, Jerry Chang-Jui KAO, Chih-Liang CHEN, Hui-Zhong ZHUANG, Jung-Chan YANG, Lee-Chung LU, Xiangdong CHEN
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Abstract
A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.
Claims20
A semiconductor device, comprising:
- a first gate-all-around field effect transistor (GAA FET) disposed over a substrate;
- a second GAA FET located at vertically different levels from the first GAA FET;
- a first power supply line connected to the first GAA FET;
- and
- a second power supply line connected to the second GAA FET, wherein:
- the first GAA FET and the second GAA FET share a gate,
- the first power supply line and the second power supply line are located at vertically different levels from each other, and
- the first power supply line is buried in an isolation insulating layer.
A semiconductor device having a standard cell, the standard cell comprising:
- a first gate-all-around field effect transistor (GAA FET) disposed over a substrate;
- a second GAA FET disposed at a vertically different level from the first GAA FET and sharing a gate with the first GAA FET;
- a first power supply line;
- a second power supply line;
- and
- a first signal line, a second signal line and a third signal line, which are disposed above the first GAA FET and the second GAA FET, wherein:
- the first, second and third signal lines are located at a same level with each other, and
- the first power supply line and the second power supply line are located at vertically different levels from each other.
A method of manufacturing a semiconductor device, the method comprising:
- forming a buried power supply line between two fin structures in an isolation insulating layer disposed over a substrate;
- forming a vertically stacked complementary MOS FET (CFET), including a first gate-all-around FET (GAA FET) and a second GAA FET stacked over the first GAA FET;
- forming an upper power line over the CFET;
- connecting a source of the first GAA FET to the buried power supply line;
- and
- connecting a source of the second GAA FET to the upper power supply line.
Dependencies are inferred from the claim text.