Through silicon via design for stacking integrated circuits

A three-dimensional (3D) integrated circuit (IC) comprising:

• a first IC die comprising a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate;
• a second IC die bonded to the first IC die, wherein the second IC die comprises a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate;
• a seal-ring structure arranged in a peripheral region of the 3D IC in the first IC die and the second IC die, wherein the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate;
• and
• a plurality of through silicon via (TSV) coupling structures arranged at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure closer to the 3D IC than the seal-ring structure, wherein the plurality of TSV coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.