Semiconductor device and manufacturing method thereof

A semiconductor device, comprising:

• a first field effect transistor (FET) including a first gate structure;
• and
• a second FET including a second gate structure having a different structure than the first gate structure, wherein:
• the first gate structure of the first FET includes:
• a first gate dielectric layer made of a dielectric material;
• a first conductive layer made of a first conductive material;
• a second conductive layer made of a second conductive material;
• and
• a first gate cap insulating layer disposed in direct contact with the first conductive layer and the second conductive layer,
• the second gate structure of the second FET includes:
• a second gate dielectric layer made of the dielectric material;
• a third conductive layer made of the first conductive material;
• a ferroelectric material layer disposed over the second gate dielectric layer and the third conductive layer;
• a fourth conductive layer disposed over the ferroelectric material layer;
• and
• a second gate cap insulating layer disposed in direct contact with the ferroelectric material layer and the fourth conductive layer,
• the second gate structure extends in a first direction,
• the ferroelectric material layer is in direct contact with the second gate dielectric layer and the third conductive layer, and has a U-shape in a cross section along a second direction crossing the first direction,
• the U-shape has a horizontal portion and vertical portions vertically extending from ends of the horizontal portion in a direction away from the substrate, and
• the second gate structure include no layer made of the second conductive material below the ferroelectric material layer.

A semiconductor device, comprising:

• a channel region, which is a part of a fin structure, disposed over a substrate and extending in a first direction;
• and
• a gate structure disposed over the channel region, wherein:
• the gate structure includes:
• a gate dielectric layer disposed over the channel region and entirely made of a high-k dielectric material;
• a lower conductive gate layer disposed over the gate dielectric layer;
• a ferroelectric material layer disposed over the lower conductive gate layer;
• an upper conductive gate layer disposed over the ferroelectric material layer;
• and
• sidewall spacers in direct contact with the gate dielectric layer and the ferroelectric material layer,
• the ferroelectric material layer fully covers and is in direct contact with an uppermost portion of the gate dielectric layer, which is a farthest part of the gate dielectric layer in a direction away from the substrate, and the lower conductive gate layer, and has a U-shape cross section along the first direction, the U-shape having a horizontal portion and vertical portions vertically extending from ends of the horizontal portion in the direction away from the substrate,
• the uppermost portion of the gate dielectric layer is located below a bottommost portion, which is a closest portion to the substrate, of the upper conductive gate layer, and
• the lower conductive gate layer does not have a U-shape and an entire upper surface of the lower conductive gate layer is in contact with the ferroelectric material layer.