System on Integrated Chips and Methods of Forming Same

A package comprising:

• a first semiconductor die;
• a first isolation material surrounding the first semiconductor die
• a second semiconductor die directly bonded to the first semiconductor die with a dielectric-to-dielectric bond;
• a second isolation material surrounding the second semiconductor die;
• a redistribution structure over the first semiconductor die and the second semiconductor die;
• and
• a conductive via electrically connecting the redistribution structure to the first semiconductor die, wherein the conductive via is separated from the second semiconductor die by the second isolation material.

A method of forming semiconductor package comprising:

• directly bonding a first semiconductor die to a second semiconductor die, without solder;
• surrounding the first semiconductor die with an isolation material;
• patterning an opening in the isolation material, wherein the opening exposes a conductive feature of the second semiconductor die;
• forming a first conductive via in the opening;
• and
• forming a redistribution structure over the first semiconductor die and the second semiconductor die, wherein the first conductive via electrically connects the redistribution structure to the conductive feature in second semiconductor die.