Fan-out semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorJung Soo KIM
Life of this patent
Estimating the term…
Abstract
A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filing at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad.
Claims20
A semiconductor package comprising:
- a connection member including a redistribution layer;
- a semiconductor chip disposed on an upper surface of the connection member, and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the connection pad is electrically connected to the redistribution layer;
- an encapsulant sealing at least a portion of the semiconductor chip;
- a plurality of conductive structures disposed on a periphery of the semiconductor chip, extending in a direction perpendicular to the upper surface of the connection member within the encapsulant, and having one ends connected to the redistribution layer and other ends opposite to the one ends;
- and
- at least one dummy structure disposed between the plurality of conductive structures, and electrically insulated from the semiconductor chip and the plurality of conductive structures,
- wherein the at least one dummy structure includes silicon, and
- wherein the at least one dummy structure is positioned on a lower level than the other end of the plurality of conductive structures.
A semiconductor package comprising:
- a connection member including a redistribution layer;
- a semiconductor chip disposed on an upper surface of the connection member, and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the connection pad is electrically connected to the redistribution layer;
- an encapsulant sealing at least a portion of the semiconductor chip;
- a plurality of conductive structures disposed on a periphery of the semiconductor chip, extending in a direction perpendicular to the upper surface of the connection member within the encapsulant, and having one ends connected to the redistribution layer and other ends opposite to the one ends;
- and
- a plurality of dummy structures disposed on a periphery of the semiconductor chip, and electrically insulated from the semiconductor chip and the plurality of conductive structures,
- wherein the plurality of dummy structures are arranged to offset from each other a plurality of warpages occurring locally in a region of the semiconductor package.
A semiconductor package comprising:
- a connection member including a redistribution layer;
- a semiconductor chip disposed on an upper surface of the connection member, and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the connection pad is electrically connected to the redistribution layer;
- an insulating layer disposed on the upper surface of the connection member;
- a plurality of conductive structures disposed on a periphery of the semiconductor chip, extending in a direction perpendicular to the upper surface of the connection member within the insulating layer, and having one end connected to the redistribution layer and other end opposite to the one end;
- and
- a plurality of dummy structures embedded in the insulating layer, and electrically insulated from the semiconductor chip and the plurality of conductive structures,
- wherein upper surfaces of the plurality of dummy structures are covered by the insulating layer.
Dependencies are inferred from the claim text.