Semiconductor package

A semiconductor package, comprising:

• a first semiconductor chip including a first semiconductor substrate, a first wiring structure on an active surface of the first semiconductor substrate, a first front surface protecting layer covering the first wiring structure and having a plurality of first front surface openings, a first rear surface protecting layer covering a non-active surface of the first semiconductor substrate, a plurality of first via electrodes penetrating through the first semiconductor substrate and the first rear surface protecting layer, and a plurality of first signal pads and a plurality of first thermal pads arranged on the first rear surface protecting layer;
• a plurality of second semiconductor chips vertically stacked on the first semiconductor chip and each including a second semiconductor substrate, a second wiring structure on an active surface of the second semiconductor substrate, a second front surface protecting layer covering the second wiring structure and having a plurality of second front surface openings, a second rear surface protecting layer covering a non-active surface of the second semiconductor substrate, a plurality of second via electrodes penetrating through the second semiconductor substrate and the second rear surface protecting layer, a plurality of signal vias and a plurality of thermal vias filling the second front surface openings and connected to the second wiring structure, and a plurality of second signal pads and a plurality of second thermal pads arranged on the second rear surface protecting layer;
• a plurality of signal bumps connecting between first and second signal pads and the plurality of signal vias;
• and
• a plurality of thermal bumps connecting between first and second thermal pads and the plurality of thermal vias,
• wherein:
• the plurality of first signal pads are connected to the plurality of first via electrodes,
• the plurality of second signal pads are connected to the plurality of second via electrodes,
• entire bottom surfaces of the plurality of first thermal pads contact the first rear surface protecting layer, and
• the entire bottom surfaces of the plurality of first thermal pads contact the second rear surface protecting layer.

A semiconductor package, comprising:

• a lower semiconductor chip including a lower semiconductor substrate, a rear surface protecting layer covering a non-active surface of the lower semiconductor substrate, a plurality of lower via electrodes penetrating through the lower semiconductor substrate and the rear surface protecting layer, and a plurality of rear surface signal pads and a plurality of rear surface thermal pads arranged on the rear surface protecting layer;
• an upper semiconductor chip including an upper semiconductor substrate, a wiring structure on an active surface of the upper semiconductor substrate, a front surface protecting layer that covers the wiring structure and has a plurality of front surface openings, and a plurality of signal vias and a plurality of thermal vias that fill the plurality of front surface openings, are connected to the wiring structure, and each have a first horizontal width and a second horizontal width;
• a plurality of signal bumps connecting between the plurality of rear surface signal pads and the plurality of signal vias and arranged at a first pitch;
• and
• a plurality of thermal bumps connecting between the plurality of rear surface thermal pads and the plurality of thermal vias and arranged at a second pitch that is greater than the first pitch, wherein:
• the plurality of signal bumps and the plurality of thermal bumps are between the lower semiconductor chip and the upper semiconductor chip,
• the plurality of rear surface signal pads are connected to the plurality of lower via electrodes, and
• the plurality of rear surface thermal pads are separated from the plurality of lower via electrodes and the lower semiconductor substrate with the rear surface protecting layer therebetween.