Structure and Process of Integrated Circuit Having Latch-Up Suppression

A method of forming an integrated circuit, the method comprising:

• forming a shallow trench isolation feature on a semiconductor substrate;
• forming a deep trench isolation feature cutting into the shallow trench isolation feature and the semiconductor substrate;
• and
• forming a n-type doped well (N-well) and a p-type doped well (P-well) in the semiconductor substrate, wherein the N-well and the P-well are disposed over the a opposite sidewalls of the deep trench isolation feature;
• forming a first metal gate and a second metal gate over the shallow trench isolation feature, wherein the first metal gate and the second metal gate are disposed over opposite side walls of the deep trench isolation feature.

A semiconductor structure, comprising:

• a semiconductor substrate;
• a deep trench isolation feature extending into the semiconductor substrate;
• a n-type doped well (N-well) disposed in the semiconductor substrate and along a first sidewall of the deep trench isolation feature;
• a p-type doped well (P-well) disposed in the semiconductor substrate adjacent to the N-well and along a second sidewall of the deep trench isolation feature;
• and
• a shallow trench isolation feature disposed over the N-well and the P-well and along the first sidewall and the second sidewall.